The central theme of my research addresses reliability and security of integrated circuits (ICs) in microprocessor-based computing systems. The use of ICs for mission-critical, safety, defense, and communication applications has highlighted the need for enhanced reliability and improved security. A holistic solution has the benefit of efficiently utilizing resources that limit system design, such as die area or power consumption. My research goals include: (1) developing architectural design techniques for soft error mitigation and (2) developing secure hardware platforms for embedded systems.
Project: Radiation-hardened microprocessors
Sponsor: Defense Threat Reduction Agency via Johns Hopkins University Applied Physics Laboratory
Extraterrestrial applications, such as satellites for both communication and global positioning or rockets for space exploration, currently receive large investments of resources to develop reliable systems. A major concern is the harsh environment of space, where high energy particles (e.g. heavy ions, protons, electrons, etc.) can damage sensitive equipment. Radiation-hardened microprocessors are required in these high-risk, space-borne applications to deliver command and control functionality to these extraterrestrial systems. The microprocessor must be protected to reduce soft faults or soft errors. My research activities will consider design techniques to mitigate the susceptibility of microprocessors to ionized particles.
Project: Soft error mitigation in digital systems
Sponsor: National Science Foundation CAREER Award
One of today's most challenging design issues is the threat of radiation-induced soft errors in CMOS digital systems. In nanometer technologies, the frequency of soft errors affects the markets of consumer electronics and networking, not just aerospace or military applications. This research aims to develop mitigation strategies that reduce the overall soft error rate while minimizing traditional cost metrics such as silicon area, power consumption, and performance degradation. The development of reliability-aware synthesis techniques is a promising approach.
Project: Malicious hardware detection
Sponsor: DARPA DSO Computer Science Study Group
The capital investment required for semiconductor foundries has limited the number of companies who fabricate their own integrated circuits (ICs). Many companies have become "fabless" and rely upon overseas foundries to manufacture their designs; these designs are then returned as packaged chips. This introduces vulnerability within the supply chain, where a design could be altered by agents with malicious intent. The trustworthiness of the hardware must be determined in a cost-effective manner to remove security vulnerabilities, such as leaking sensitive data or creating a hidden backdoor in a microprocessor to enable a system hijack. This project investigates the effectiveness of our signature-based malicious hardware detection within cryptographic hardware for implementations using low-power circuit techniques.
Project: Low-power hardware platform for secure embedded systems
Sponsor: National Science Foundation via the Team for Research in Ubiquitous Secure Technology (TRUST)
The goal of this project is to develop an ultra low-power hardware platform for secure embedded sensing, with medical instrumentation as an initial target application. This work is in collaboration with Prof. Rajit Manohar at Cornell University using asynchronous circuits. We plan to develop a combined hardware-software co-design approach to tackle the problem of information security. The challenges include supporting both long-lifetime operation and strong encryption. We also address the development of methodologies that limit side-channel attacks. These challenges will be addressed using a combination of hardware and software techniques to enable small, un-tethered wireless sensors for medical monitoring and diagnosis. The long-term goal of the project is to design and fabricate a custom ultra low-power microprocessor with security support.